Brion Computational Lithography Seminar

IC geometry reduction, despite the repeated assertions that the reduction is getting to its limit, is still keeping its rapid pace solidly. Under the circumstances, coupled with the delay in defining the NGL, increasing NA and suppressing K1 factor of optical system of lithography equipment to enable innovative extension of 193nm lithography are demanded strongly by the semiconductor industry. 　Increasing number of systematic defects, due to imperfections of RET/OPC and reticles(photo-masks) coming from substantially reduced latitude of dose/DOF in the course of pursuing challengeable resolution limit, however, is becoming an extremely serious problem. In order to solve this problem, it is clearly crucial then to prevent the flow of systematic defects to the final wafer fab. process by checking such defect causes and preparing verified solutions to the systematic problems at the stage of RET/OPC design and subsequent mask making.
Pattern accuracy requirements are also extremely demanding. In case of 65nm generation, majority of error sources are attributed to RET/OPC and mask.　Further geometry reduction no doubt will make the errors attributed to RET/OPC and photo-mask even more serious requiring substantial and immediate accuracy improvements in those areas.
Seeking solutions across the board in overall semiconductor industry, therefore is demanded to overcome the problems associated with the non-stop geometry reduction. It has become quite clear lately that the problems can be effectively addressed by computational lithography* combining respective semiconductor process elements and technologies across the board by use of the latest lithography simulation methodologies with substantially increasing computation speed.
At this seminar, IDMs will report the status of their study of this emerging technology, and based on the reports we want to discuss the impending integration of computational lithography and respective semiconductor technology elements to seek future requirements for computational lithography, mask , photolithography equipment, metrology and inspection gears, among others. It is foreseen that connecting the computational lithography with the up-stream device designing should bring about improved design process efficiency as well, and lively and vigorous discussion on this subject is also expected.　Sincerely hope that certain new flow and direction of the non-stop geometry reduction and underpinning technologies can be found at the Seminar, and really wish many of you join us.

　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 Tadahiro Takigawa

* “Computational Lithography” is the term used to mean lithography simulations taking into account all the conceivable IC process variables, which has become practically feasible thanks to the recent rapid computation speed improvement

Program of Brion Seminar

■【Opening Talk】 Brion Technologies Inc. & Brion Technologies KK Chairman,Board of Directors,Japan Operations Tadahiro Takigawa, Ph.D ＜10:00〜10:10＞ ■【Computational Lithography】 Brion Technologies Inc. Mr.Jun Ye ＜10:10〜10:50＞ ■【Device and computational Lithography】 Toshiba Corporation Semiconductor Company Mr.Souichi Inoue ＜10:50〜11:30＞ ■【Tachyon application to Lithography】 NEC Electronics Corporation Mr.Toshiaki Yanagihara ＜11:30〜12:10＞ 《Lunch》＜12:10〜13:30＞ ■【Scanner and Computational Lithography】 Nikon Mr.Tomoyuki Matsuyama ＜13:30〜14:10＞ ■【Mask and Computational Lithography】 Dai Nippon Printing 【※A lecturer is undecided】 ＜14:10〜14:50＞ 《Coffee break》＜14:50〜15:10＞ ■【Metrology and Computational Lithograhy】 Hitachi High-Technologies Corporation 【※A lecturer is undecided】 ＜15:10〜15:50＞ ■【Common Modeling Environment for Lithography】 MAGMA ＜15:50〜16:30＞ ■【Brion Solution】 Brion Technologies Inc. Vice President,Product Marketing Mr.Hua Yu Liu ＜16:30〜17:10＞ ■【Closing Talk】 ＜17:10〜17:15＞ 《Cocktail Party》＜17:30〜19:30＞

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